The present invention relates to a digital multiplication circuit for multiplying a signed multiplier by a signed multiplicand represented in terms of the two's complement based on a binary code.
The multiplicand Y and the multiplier X which each have n bits and are represented in terms of the two's complement can be expressed by the following equation: ##EQU1## where X* and Y* respectively indicate the numeral sections of binary codes X and Y of the type represented in terms of the two's complement, and accordingly the X* and Y* can be expressed by the following equations: ##EQU2## Further, X.sub.S and Y.sub.S are sign bits, and become "0" when positive and become "1" when negative.
The product X.multidot.Y can be given by the following equation: ##EQU3##
Assume that the binary numerals which are obtained by inverting the bits of the X* and Y* are respectively represented by X* and Y*, and the eq. (3) can be rewritten as below. ##EQU4##
As evident from the above eq. (4), in order to obtain the product X.multidot.Y, it is necessary to correct the first term (X*.multidot.Y*) with the second and following terms. In other words, it is necessary to add the terms (X.sub.S .multidot.Y*.multidot.2.sup.n-1), (Y.sub.S .multidot.X*.multidot.2.sup.n-1), (X.sub.S .multidot.2.sup.n-1) and (Y.sub.S .multidot.2.sup.n-1) to the first term (X*.multidot.Y*) and to further add the last term 2.sup.2n-2 .multidot.(X.sub.S .multidot.Y.sub.S -X.sub.S -Y.sub.S). Since the last term 2.sup.2n-2 .multidot.(X.sub.S .multidot.Y.sub.S -X.sub.S -Y.sub.S) should, however, become 0 or -2.sup.2n-2, the addition of the term 2.sup.2n-2 (X.sub.S .multidot.Y.sub.S -X.sub.S -Y.sub.S) can be generally executed by setting the logical sum of the sign bits X.sub.S and Y.sub.S at the (2n-1)th bit position, i.e., the next bit position of the most significant bit position, of the added result of the term {(X*.multidot.Y*)+X.sub.S .multidot.Y*.multidot.2.sup.n-1 +Y.sub.S .multidot.X*.multidot.2.sup.n-1 +X.sub.S .multidot.2.sup.n-1 +Y.sub.S .multidot.2.sup.n-1 }.
The following conditional inequalities can be obtained from the eq. (1) and (2): ##EQU5##
The following conditional inequality can be introduced from the above conditional inequalities (5) and (6). ##EQU6##
In other words, when the most significant bit M0 of the product X.multidot.Y is used as a sign bit and the numeral section of the product X.multidot.Y is represented by the bit M1 to M(2n-1), the following conditional inequality can be obtained: ##EQU7##
In the inequality (8) described above, "0" in the most significant bit position to the left side indicates that the binary numeral of the following (2n-1) bits of the left side is positive, while "1" in the most significant position of the right side indicates that the (2n-1)-bit binary numeral represented in terms of the two's complement except the most significant bit "1" of the right side is negative. Further, "1" in the n-th bit position of the right side represents 2.sup.n-1 in the right side of the inequality (7). In the inequality (7) described above, X.multidot.Y=2.sup.2n-2 can be obtained in case of X=Y=-2.sup.n-1. That is, there is no possibility that the most significant bit M0 of the product X.multidot.Y becomes "0" and at the same time the bit M1 becomes "1" in the (2n-1)th bit position except in case of X=Y=-2.sup.n-1.
In addition, the following inequality (9) can also be obtained from the inequality (7): ##EQU8##
As evident from the inequality (9) described above, there is as well no possibility that, when the most significant bit M0 of the product X.multidot.Y is "1", the bit M1 in the (2n-1)th bit position becomes "0".
According to the above technical background, in the conventional array type digital multiplication circuit for executing the multiplication of the signed binary numerals X and Y of n bits indicated by the two's complement, input binary data X and Y are so limited as to exclude the case where the most significant bit M0 of the multiplied result and the bit M1 in the (2n-1)th bit position do not take the same value, i.e., where the binary numerals X and Y both take the value of -2.sup.n-1. However, such a limit on the input binary data would restrict the function of the digital multiplication circuit. It has been considered that a complicated input circuit would be required in order to operate this digital multiplication circuit normally even when input binary data X and Y are simultaneously -2.sup.n-1.